A hardware description language (HDL) is a specialized computer language used to describe the structure, design and operation of electronic circuits, and most commonly, digital logic circuits. A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis, simulation, and simulated testing of an electronic circuit. It also allows for the compilation of an HDL program into a lower level specification of physical electronic components, such as the set of masks used to create an integrated circuit. HDLs form an integral part of Electronic design automation systems.
HDLs are processed by a compiler (usually called a synthesizer). For HDLs, ‘compiler’ refers to synthesis, a process of transforming the HDL code listing into a physically realizable gate netlist. The netlist output can take any of many forms: a “simulation” netlist with gate-delay information, a “handoff” netlist for post-synthesis place and route, or a generic industry-standard EDIF format.
A compiler is a program that transforms source code written in a high-level programming language to a lower level language (e.g., assembly language or machine code) in order to create an executable program. FIG. 1 illustrates a typical flowchart of a compiler. Specifically, this figure describes a process 100 that transforms source code written in a high level programming language to machine code. The process 100 begins by using, at block 105, a lexical analyzer to convert string of characters in the source code into string of tokens.
At block 110, the process 100 uses a parser to construct a parse tree based on the string of tokens. At block 115, the process 100 uses a semantic analyzer to add semantic information to the parse tree. At block 120, the process 100 uses a translator to convert the parse tree to low-level intermediate code.
At block 125, the process 100 uses an optimizer to optimize the low-level intermediate code. At block 130, the process 100 converts the optimized low-level intermediate code to machine code. An optimizing compiler is a compiler that tries to minimize or maximize some attributes of an executable computer program. The most common requirement is to minimize the time taken to execute a program; a less common one is to minimize the amount of memory occupied. Compiler optimization is generally implemented using a sequence of optimizing transformations, algorithms that take a program and transform it to produce a semantically equivalent output program that uses fewer resources.
Code coverage is a measure used to describe the degree to which the source code of a program is tested by a particular test suite. Generally, a program with high code coverage has been more thoroughly tested and has a lower chance of containing software bugs than a program with low code coverage. Sometimes in electronic design automation, 100% code coverage of a design written in HDL is required as part of the design signoff process.
In electronic design, code coverage targets are inferred from designs written in HDL. Designs typically contain many inferred coverage targets (combinations of values, executable lines, value transitions, etc.) that cannot be reached. These unreachable coverage targets take up resources in electronic design and require a substantial amount of time to test in order to achieve high code coverage and coverage closure. Currently, unreachable coverage targets that cannot be removed automatically must be identified and removed manually, which is a time consuming and error prone process.